The present invention relates to a convolutional interleaver, a convolutional deinterleaver, a convolutional interleaving method, and a convolutional deinterleaving method, which are required for digital transmission of satellite broadcasting, ground wave broadcasting, CATV broadcasting, etc, and for reading/writing of a storage unit such as a hard disk.
A convolutional deinterleaving method is effective as a countermeasure against burst errors.
Burst errors will be briefly described taking satellite broadcasting as an example. A broadcast wave from a broadcasting station on earth is transmitted to a satellite and relayed at the satellite to a satellite broadcast receiver provided in home.
The wave transmitted from the broadcasting station through the satellite to home is subjected to interference by thunder, rain or the like in the transmission path and while the wave is subjected to such interference, errors occur in data. These errors are called xe2x80x9cburst errorsxe2x80x9d.
In digital transmission, information for error correction is added to the original data in advance and, therefore, it is possible to correct errors so long as the errors are within a predetermined range of bits in each segment. However, since burst errors occur continuously over the range, it is impossible to correct burst errors.
So, as a countermeasure against burst errors, data to be transmitted are temporally dispersed in advance. To be specific, by temporally dispersing the data at the transmitting end, even when burst errors occur in the process of transmission, the burst errors are dispersed when recovering the temporal, positions of the dispersed data at the receiving end, whereby the burst errors can be limited within a correctable range of bit number in each data unit.
In this way, a method of temporally dispersing data to be transmitted is xe2x80x9cconvolutional interleavingxe2x80x9d, and a method of restoring the temporal positions of the dispersed data at the receiving end is xe2x80x9cconvolutional deinterleavingxe2x80x9d.
There has been proposed a convolutional interleaver used for the above-mentioned purpose by, for example, Japanese Published Patent Application No. Hei. 7-170201.
FIG. 13 is a block diagram illustrating a convolutional interleaver disclosed in the above-mentioned prior art. With reference to FIG. 1-3, input data which is serially input to the interleaver through an input terminal 1000 is read into a serial-parallel conversion shift register 3000 according to a high-speed clock input through a clock input terminal 2000, wherein the serial data is converted to N stages of parallel signals.
Then, the serial-to-parallel conversion shift register 3000 outputs the N stages of parallel signals together with the clock signal which has been subjected to 1/N frequency division by an N-stage frequency divider 4000. The N stages of parallel signals are respectively input to shift registers 5001, 5002, 5003, . . . , 500 (Nxe2x88x921) which give delays to input data thereof, wherein those parallel signals are given delay times in proportion to the stage numbers of the respective shift registers, M, 2M, 3M, . . . , (Nxe2x88x921) M. Then, the N stages of parallel signals which have been delayed by the shift registers 5001, 5002, 5003, . . . , 500 (Nxe2x88x921) are input to a parallel-to-serial conversion shift register 6006 to be converted to a serial signal. The serial signal is output from an output terminal 7000 as data obtained by interleaving the data at the input terminal 1000.
FIG. 14 is a block diagram illustrating a convolutional deinterleaver for deinterleaving the data interleaved by the convolutional interleaver shown in FIG. 13. With reference to FIG. 14, input data applied to an input terminal 11000 is read into a serial-to-parallel conversion shift resister 13000 according to a high-speed clock input through a clock input terminal 12000, wherein the input data is converted to N stages of parallel signal.
Then, the serial-to-parallel conversion shift register 11,000 outputs the N stages of parallel signals together with the clock signal which has been subjected to 1/N frequency division by an N-stage frequency divider 14000. The N stages of parallel signals are respectively input to shift registers 900 (Nxe2x88x921), . . . , 9003, 9002, 9001 which give delays to input data, wherein these parallel signals are given delay times in proportion to the stage numbers of the respective shift registers, (Nxe2x88x921) M, . . . , 3M, 2M, M. Then, the N stages of parallel signals respectively delayed by the shift registers 900 (Nxe2x88x921), . . . , 9003, 9002, 9001 are input to a parallel-to-serial conversion shift register 16000 to be converted to a serial signal. The serial signal is output from an output terminal 17000 as data obtained by deinterleaving the data at the input terminal 11000.
As described above, the convolutional interleaver shown in FIG. 13 or the convolutional deinterleaver shown in FIG. 14 requires multiple stages of shift registers, resulting in an increase in the circuit scale.
Meanwhile, as a prior art which can solve the above-described problem, a convolutional interleaver using a RAM has been proposed.
The structure of the convolutional interleaver is shown in FIG. 15. With reference to FIG. 15, the convolutional interleaver comprises a single port RAM 13, an input data control means 9, a select signal generating means 10, a RAM control means 11, an address generating means 3, a writing means 12, a reading means 14, and an output signal selector 15. The single port RAM 13 outputs data to the reacting means 14. The input data control means 9 outputs input of the convolutional interleaver to the input data writing means 12 and the output signal selector 15. The select signal generating means 10 outputs a control signal to the lower address selector 7 and the RAM control means 11. The RAM control means 11 outputs a control signal to the RAM 13 and the output signal selector 15. The address generating means 3 outputs an address to the writing means 12 and the reading means 14. The writing means 12 outputs an address and data to the RAM 13. The reading means 14 outputs an address and data to the RAM 13. The output signal selector 15 generates an output signal of the convolutional interleaver.
The address generating means 3 comprises an upper address generating means 4, a lower address generating means 5, and an output timing adjusting means 8. The upper address generating means 4 outputs an upper address for each channel to the output timing adjusting means 8 and the reading means 14. The lower address generating means 5 outputs a lower address for each channel to the output timing adjusting means 8 and the reading means 14.
The lower address generating means 5 comprises a counter unit 6 and a lower address selector 7. The counter unit 6 outputs a lower address For each channel to the lower address selector 7. The counter unit 6 comprises counters 60xcx9c6C corresponding to channels ch0xcx9cchC, respectively. The lower address selector 7 outputs a lower address to the output timing adjusting means 8.
Both of the select signal generating means 10 and the address generating means 3 shown in FIG. 15 serve as an input side selector in the operation principle which is later described using FIG. 16. On the other hand, both of the output signal selector 15 and the address generating means 3 serve as an output side selector in the operation principle.
Hereinafter, the operation principle of the convolutional interleaver shown in FIG. 15 will be described with reference to FIG. 16.
In FIG. 16, reference numeral 102 denotes a single port RAM which synchronizes with a clock of frequency of f, and numerals 100 and 101 denote selectors disposed at the input side and the output side of the single port RAM 102, respectively. The single port RAM 102 has multiple stages of storage areas corresponding to the respective channels and each having a bit width b, and the number of the storage areas is equal to xe2x80x9cdepth (m)xc3x97number of channels (N)xe2x80x9d wherein m is the number of data in bit width units, and 0xe2x89xa6Nxe2x89xa6C. The selectors 100 and 101 select the channels circularly and synchronously with each other. To be specific, these selectors 100 and 101 start from ch0, successively increment the channel number, and return to ch0, when reaching chC to repeat the same operation as above.
Initially, both the selectors 100 and 101 select channel ch0. Since no delay element exists at this channel, the signal of ch0, travels through the convolutional interleaver without being delayed.
Next, the selectors 100 and 101 select ch1. Since an FIFO is implemented by RAM (storage area) 102-0 at this channel, a signal delayed by this RAM 102-0 is output.
Thereafter, in similar manner, the selectors 100 and 101 successively select ch2, ch3, . . . , chNxe2x88x921, whereby signals which are delayed by 2, 3, . . . , Nxe2x88x921( greater than 1) times as much as the delay at ch1 by RAM 102-1, RAM 102-2, . . . , RAM 102-(Nxe2x88x922), are output, respectively.
Then, the selectors 100 and 101 select chN. At this channel, a signal delayed by N( greater than 1) times as much as the delay at ch1 by RAM 102-(Nxe2x88x921) is output.
Then, the selectors 100 and 101 select chC. At this channel, a signal delayed by C( greater than N) times as much as the, delay at ch1 by RAM 102-(Cxe2x88x921) is output.
At the next point of time, the selectors 100 and 101 select ch0 again to repeat the above-mentioned operation.
As described above, the convolutional interleaver reads the oldest data from the storage area of the RAM corresponding to the selected channel, writes the input data of the convolutional interleaver into the address from which the data has been read, and outputs the read data as the output of the convolutional interleaver.
By repeating the above-mentioned processing, the convolutional interleaver performs convolutional interleaving for the input data.
Hereinafter, a description is given of the operation of the convolutional interleaver shown in FIG. 15.
The convolutional interleaver captures input data to be interleaved from the input data terminal 1 by using the input data control means 9, and writes the data into the RAM 13 by using the writing means 12. At this time, for the b-bit data of the respective channels ch0xcx9cchC, the counters 60xcx9c6C of the lower address generating means 5 corresponding to these channels count the lower addresses of the RAM 13, and the lower address selector 7 selects one of these lower addresses. The lower address so selected and the upper address of the RAM 13 output from the upper address generating means 4 are input to the output timing adjusting means 8, wherein their output timings are adjusted, and then these addresses are input to the writing means 12 to give a write address of the RAM 13.
With respect to the data of ch0, the input data control means 9 transmits this data not through the RAM 13 but directly to the output signal selector 15. The RAM control means 11 selects this non-delayed data which has been sent from the input data control means 9, directly to the output signal selector 15, and outputs this data from the output terminal 2 to the outside.
Further, for the data of ch1xcx9cchNxcx9cchC, storage areas, the sizes of which gradually increase in order of these channels, are set in the RAM 13 by the upper address generating means 4. Addresses inside the respective storage areas are generated by the counter unit 6 of the lower address generating means 5, and these addresses are selected by the lower address selector 7 every time the selector 7 successively selects the corresponding channels. With respect to the channels to which b-bit data are sequentially applied, the following operation is performed on each storage area foe each channel. That is, the data is written in an address in the storage area and, at the next point of time, the data is read from the address to be written in the next address. In this way, gradually increasing delay times are given to the data of channels ch1xcx9cchNxcx9cchC, respectively.
Next, a description will be given of the structure of a convolutional deinterleaver which deinterleaves the data interleaved by the convolutional interleaver shown in FIG. 15, by using FIG. 17.
With reference to FIG. 17, the convolutional deinterleaver comprises a single port RAM 33, an input data control means 29, a select signal generating means 30, a RAM control means 31, an address generating means 23, a writing means 32, a reading means 34, and an output signal selector 35. The single port RAM 33 outputs data to the reading means 34. The input data control means 29 outputs input data of the convolutional deinterleaver to the input data writing means 32 and the output signal selector 35. The select signal generating means 30 outputs a control signal to the lower address selector 27 and the RAM control means 31. The RAM control means 31 outputs a control signal to the RAM 33 and the, output signal selector 35. The address generating means 23 outputs an address to the writing means 32 and the reading means 34. The writing means 32 outputs an address and data to the RAM 33. The reading means 34 outputs an address and data to the RAM 33. The output signal selector 35 generates an output signal of the convolutional deinterleaver
The address generating means 23 comprises an upper address generating means 24, a lower address generating means 25, and an output timing adjusting means 28. The upper address generating means 24 outputs an upper address for each channel to the output timing adjusting means 28 and the reading means 34. The lower address generating means 25 outputs a lower address for each channel to the output timing adjusting means 28 and the reading means 34.
The lower address generating means 25 comprises a counter unit 26 and a lower address selector 27. The counter unit 26 outputs a lower address for each channel to the lower address selector 27. The counter unit 26 comprises count 260xcx9c26C corresponding to channels ch0-chC, respectively. The lower address selector 27 outputs a lower address to the output timing adjusting means 28.
Both of the select signal generating means 30 and the address generating means 23 serve as an input side selector in the operation principle is later described using FIG. 18. On the other hand, both of the output signal selector 35 and the address generating means 23 serve as an output side selector in the operation principle.
Hereinafter, the operation principle of the convolutional deinterleaver will be described with reference to FIG. 18.
In FIG. 18, reference numeral 1112 denotes a port RAM which synchronies with a clock of frequency of and numerals 1110 and 1111 denote selectors disposed at the input side and the output side of the single port RAM 1112, respectively. The single port RAM 1112 has multiple stages of storage areas corresponding to the respective channels and each having a bit width b, and the number of the storage areas is equal to xe2x80x9cdepth (m)xc3x97(maximum channel numbered(C)xe2x88x92channel number(N)-1)xe2x80x9d_0 wherein 0xe2x89xa6Nxe2x89xa6C. The selectors 1110 and 1111 select the channels circularly and synchronously with each other. To be specific, these selectors 1110 and 1111 start from ch0, successively increment the channel number, and return to ch0 when reaching chC to repeat the same operation as above.
Initially, both of the selectors 1110 and 1111 select ch0. At this channel, a signal which is delayed by C( greater than 1) times as much as the delay at ch1 of the convolutional interleaver by RAM 1112-0, is output.
Next, the selectors 1110 and 1111 select ch1. At this channel, a signal which is delayed by (Cxe2x88x921) times as much as the delay at ch1 of the convolutional interleaver by RAM 1112-1, is output.
Thereafter, in a similar manner, the selectors 1110 and 1111 select ch2, ch3, . . . , chNxe2x88x921 and signals which are delayed by (Cxe2x88x922), (Cxe2x88x923), . . . , (Cxe2x88x92(Nxe2x88x921))( greater than 1) times as much as the delay at ch1 of the convolutional interleaver by RAM 1112-2, RAM 1112-3, . . . , RAM 1112-(Nxe2x88x921), respectively, are output.
Then, the selectors 1110 and 111 select chN. At this channel, a signal which is delayed by (Cxe2x88x92N) times as much as the delay at ch1 of the convolutional interleaver by RAM 1112-N, is output.
Thereafter, the selectors 1110 and 111 select chC. Since no delay element exists at this channel, the signal at chC travels through the convolutional deinterleaver without being delayed.
At the next point of time, both of the selector 1110 and 1111 select ch0 again to repeat the above-mentioned operation.
As described above, the convolutional deinterleaver reads the oldest data from the storage area of the RAM corresponding to the selected channel, writes the input data of the convolutional deinterleaver into the address from which the data has been read, and outputs the read data as the output of the convolutional deinterleaver.
By repeating the above-mentioned processing, the input data is restored into the same data format as that before the convolutional interleaving.
Next, a description is given of the operation of the convolutional deinterleaver.
The convolutional deinterleaver captures input data to be deinterleaved from the input data terminal 21 by using the input data control means 29 and then writes the data into the RAM 33 by using the writing means 32. At this time, for the b-bit data of the respective channels ch0xcx9cchNxcx9cchC, the counters 260xcx9c26Nxcx9c26C of the lower addresses generating means 25 corresponding to these channels count the lower addresses of the RAM 33, and the lower address selector 27 selects one of these lower addresses. The lower address so selected and the upper address of the RAM 33 output from the upper address generating means 24 are input to the output timing adjusting means 28, wherein their output timings are adjusted, and then these addresses are input to the writing means 32 to give a write address of the RAM 33.
With respect to the data of chC, the input data control means 29 transmits this data not through the RAM 33 but directly to the output signal selector 35. The RAM control means 31 selects this non-delayed data which has been sent from the input data control means 29 directly to the output signal selector 35, and outputs this data from the output terminal 22 to the outside.
Further, for the data of ch1xcx9cchNxcx9cchC, storage areas, the sizes of which gradually decrease in order of these channels, are set in the RAM 33 by the upper address generating means 24. Addresses inside the respective storage areas are generated by the counter unit 26 of the lower address generating means 25, and these addresses are selected by the lower address selector 27 every time the selector 27 successively selects the corresponding channels. With respect to the channels to which b-bit data are sequentially applied, the following operation is performed on each storage area for each) channel. That is, the data is written in an address in the storage area and, all, the next point of time, the data is read from the address to be written in the next address. In this way, gradually decreasing delay times are given to the data of channels ch0xcx9cchNxcx9cchCxcx9c1, respectively.
Thereby, the channels ch0xcx9cchNxcx9cchC are given gradually decreasing delay times by the convolutional deinterleaver shown in FIG. 16 while these channels have been given gradually increasing delay times by the convolutional interleaver shown in FIG. 15. Synthetically, the same delay time is given to all the channels, whereby the data array which has been interleaved by the convolutional interleaver shown in FIG. 15 is deinterleaved (restored) by the convolutional deinterleaver shown in FIG. 16.
By the way, when a digital system is constructed as an integrated circuit, it as required that as many circuits as possible are mounted on the same integrated circuit and the same is required of a system including a convolutional interleaver and a conventional deinterleaver. Therefore, in this kind of system, further reductions in area and power consumption are required of the convolutional interleaver and deinterleaver.
An object of the present invention is to provide a convolutional interleaver, a convolutional deinterleaver, a convolutional interleaving method, and a convolutional deinterleaving method, which ran realize reductions in area and power consumption by optimizing a RAM control system.
Other objects and advantages of the invention will become apparent from the detailed description that follows. The detailed description and specific embodiments described are provided only for illustrates n since various additions and modifications within the scope of the invention will be apparent to these of skill in the art from the detailed description.
According to a first aspect of the present invention, there is provided a convolutional interleaver performing convolutional interleaving for a data group in which the input/output data width is b bits, the depth, i.e., the number of data-in bit width units, is m, the number of channels is n, and the maximum channel number is C (n=integer satisfying the relation 0xe2x89xa6nxe2x89xa6C, b,m,C=natural numbers), and this interleaver includes delay means comprising first and second delay units and performing a delay of nT for data of the n-th channel (T=a predetermined amount of delay, T greater than 0). The first delay unit performs a delay of is (S=a predetermined amount of delay, 0 less than Sxe2x89xa6T) for the i-th group amongst groups into which all the channels are grouped such that each group comprises at most k channels, the i-th group comprising channels from the ik-Uh channel to the ((ixe2x88x921)kxe2x88x921)-th channel (k=natural number not larger than C, i=integer satisfying the relation 0xe2x89xa6ixe2x89xa6(integer part of (C/k)), (i+1)kxe2x88x921xe2x89xa6C). The second delay unit performs a delay equivalent to a deficiency in the delay of the first delay unit for the delay of nT to be given to the data of the n-th channel. Therefore, delays to be commonly generated between channels in each group are generated together by the first delay unit, and delays including differences in delays between the channels are individually generated by the second delay unit, whereby control and structure of the delay means can be simplified.
According to a accord aspect of the present invention, in the convolutional interleaver of the first aspect, C is an odd number, k is 2, S and T satisfy the relation S=T, and the second delay unit performs a delay of T for the (2h+1)-th channel (h=integer satisfying the relation 0xe2x89xa62h+1xe2x89xa6C) and does not perform a delay for the 2h-th channel. Therefore, delays to be commonly generated between two channels in each group are generated together by the first delay unit, and a difference in delays between the two channels is generated for only one of these two channels by the second delay unit, whereby control and structure of the delay means can be simplified.
According to a third aspect of the present invention, there is provided a convolutional interleaver performing convolutional interleaving for a data group in which the input/output data width is b bits, the depth i.e., the number of data in bit width units, is m, the number of channels is n, and the maximum channel number is C (n=integer satisfying the relation 0xe2x89xa6nxe2x89xa6C, b,m,C=natural numbers), and the interleaver comprises: first storage means having a data width of jxc3x97b bits (j=natural number not less than 2); input data control means for distributing input data of the convolutional interleaver to bit connecting means, or second storage means, or output data control means; the second storage means for delaying input data from the input data control means; the bit connecting means for connecting input data from the input data control means and input data from the second storage means to generate data to be input to the first storage means having a data width of jxc3x97b bits; address generating means for generating addresses of the first storage means; bit separating means for converting output data from the first storage means into data having a data width of b bits and to be output from the convolutional interleaver; and the output data control means for outputting output data from the bit separating means to the outside of the convolutional interleaver. Therefore, the RAM address generating means is optimized, whereby the area of the address generating circuit is minimized and the frequency of access to the RAM is reduced. Thereby, convolutional interleaving can be performed with the minimum power consumption and, moreover, it can be performed even with a RAM operating at a low frequency.
According to a fourth aspect of the present invention, the convolutional interleaver of the third aspect comprises: the address generating means performing address generation such that the first storage means performs a delay of iS (S=a predetermined amount of delay, 0 less than S) for the i-th group amongst groups into which all the channels are grouped such that each group comprises at most k channels, the i-th group comprising channels from the ik-th channel to the ((i+1)kxe2x88x921)-th channel (k=natural number not larger than C, i=integer satisfying the relation 0xe2x89xa6ixe2x89xa6(integer part of (C/k)), (i+1)kxe2x88x921xe2x89xa6C); the second storage means having a capacity sufficient to perform a delay equivalent to a deficiency in the delay of the first storage means for the delay of nT (T=a predetermined amount of delay, Sxe2x89xa6T) to be given to the data of the n-th channel; and switching means for successively switching the channels every time data of b bits and depth m is input, such that the channel of data input to the first storage means and the second storage means is identical in channel number to the channel of the data output from the first storage means. Therefore, the same effects as mentioned above are achieved.
According to a fifth aspect of the present invention, in the convolutional interleaver of the fourth aspect, C is an odd number, k is 2, S and T satisfy the relation S=T, and the second delay unit performs a delay of T for the (2h+1)-th channel (h=integer satisfying the relation 0xe2x89xa62h+1xe2x89xa6C) and does not perform a delay for the 2h-th channel. Therefore, the same effects as mentioned above are achieved.
According to a sixth aspect of the present invention, in the convolutional interleaver of the third aspect, the second storage means and the first storage means are constructed by the same kind of storage means. Therefore, the same effects as mentioned above are achieved.
According to a seventh aspect of the present invention, in the convolutional interleaver of the third aspect, the first storage means is constructed by a RAM. Therefore, the same effects as mentioned above are achieved.
According to an eighth aspect of the present invention, in the convolutional interleaver of the seventh aspect, the RAM has j pieces of input/output ports (j=natural number not less than 2). Therefore, the same effects as mentioned above are achieved.
According to a ninth aspect of the present invention, there is provided a convolutional deinterleaver performing convolutional deinterleaving for a data group in which the input/output data width, is b bits, the depth, i.e., the number of data in bit width units, is m, the number of channels is n, and the maximum channel number is C (n=integer satisfying the relation 0xe2x89xa6nxe2x89xa6C, b,m,C=natural numbers), . . . , and the deinterleaver includes delay means comprising first and second delay units and performing a delay of (Cxe2x88x92n)T for data of the n-th channel (T=a predetermined amount of delay, T=0). The first delay unit performs a delay of (Cxe2x88x92i)S (Sxe2x80x94a predetermined amount of delay, Cxe2x89xa6Sxe2x89xa6T) for the i-th group amongst groups into which all the channels are grouped such that each group comprises at most k channels, the i-th group comprising channels from the ik-th channel to the (i+1)kxe2x88x921)-th channel (k=natural number not larger than C, i=integer satisfying the relation 0xe2x89xa6ixe2x89xa6(integer part of (C/k)), (i+1)kxe2x88x921xe2x89xa6C), and the second delay unit performs a delay equivalent to a deficiency in the delay of the first delay unit for the delay of (Cxe2x88x92n)T to be given to the data of the n-th channel. Therefore, delays to be commonly generated between channels in each group are generated together by the first delay unit, and delays including differences in delays between the channels are individually generated by the second delay unit, whereby control and structure of the delay means can be simplified.
According to a tenth aspect of the present invention, in the convolutional deinterleaver of the ninth aspect, C is an odd number, k is 2, S and T satisfy the relation S=T, and the second delay unit performs a delay of T for the (2h+1)-th channel (h=integer satisfying the relation 0xe2x89xa62h+1xe2x89xa6C) and does not perform a delay for the 2h-th channel. Therefore, delays to be commonly generated between two channels in each group are generated together by the first delay unit, and a difference in delays between the two channels is generated for only one of these two channels by the second delay unit, whereby control and structure of the delay means can be simplified.
According to an eleventh aspect of the present invention, there is provided a convolutional deinterleaver performing convolutional deinterleaving for a data group in which the input/output data width is b bits, the depth, the number of data in bit width units, is m, the number of channels is n, and the maximum channel number is C (n=integer satisfying the relation 0xe2x89xa6nxe2x89xa6C, b,m,C=natural numbers), and the deinterleaver comprises: first storage means having a data width of jxc3x97b bits (j=natural number not less than 2); input data control means for distributing input data of the convolutional deinterleaver to bit connecting means, or second storage means, or output data control means the second storage means for delaying input data from the input data control means; the bit connecting means for connecting input data from the input data control means and input data from the second storage means to generate data to be input to the first storage means having a data width of jxc3x97b bits; address generating means for generating addresses of the first storage means; bit separating means for converting output data from the first storage means into data having a data width of b bits and to be output from the convolutional deinterleaver; and the output data control means for outputting output data from the bit separating means to the outside of the convolutional deinterleaver. Therefore, the RAM address generating means is optimized, whereby the area of the address generating circuit is minimized and the frequency of accesses to the RAM is reduced. Thereby, convolutional deinterleaving can be performed with the minimum power consumption and, moreover, it can be performed even with a RAM operating at a low frequency.
According to a twelfth aspect of the present invention, the convolutional deinterleaver of the eleventh aspect comprises the address generating means performing address generation such that the first storage means performs a delay of (Cxe2x88x92i)S (S=a predetermined amount of delay, 0 less than S) for the i-th group amongst groups into which all the channels are grouped such that each group comprises at most k channels, the i-th group comprising channels from the ik-th channel to the ((i+1)kxe2x88x921)-th channel (k=natural number not larger than C, i=integer satisfying the relation 0xe2x89xa6ixe2x89xa6(integer part of (C/k)), (i+1) kxe2x88x921xe2x89xa6C; the second storage means having a capacity sufficient to perform a delay equivalent to a deficiency in the delay of the first storage means for the delay of (Cxe2x88x92n)T (T=a predetermined amount of delay, Sxe2x89xa6xcfx84) to be given to the data of the n-th channel; and switching means for successively switching the channels every time data of b bits and depth m is input, such that the channel of data input to the first storage means and the second storage means is identical in channel number to the channel of the data output from the first storage means. Therefore, the same effects as described above are achieved.
According to a thirteenth aspect of the present invention, in the convolutional deinterleaver of the twelfth aspect, C is an odd number, k is 2, S and T satisfy the relation S=T, and the second delay unit performs a delay of xcfx84 for the (2h+1)-th channel (h=integer satisfying the relation 0xe2x89xa62h+1xe2x89xa6C) and does not perform a delay for the 2h-th channel. Therefore, the same effects as described above are achieved.
According to a fourteenth aspect of the present invention, in the convolutional deinterleaver of the eleventh aspect, the second storage means and the first storage means are constructed by the same kind of storage means. Therefore, the same effects as described above are achieved.
According to a fifteenth aspect of the present invention, in the convolutional deinterleaver of the eleventh aspect, the first storage means is constructed by a RAM. Therefore, the same effects as described above are achieved.
According to a sixteenth aspect of the present invention, in the convolutional interleaver of the fifteenth aspect, the RAM has j pieces of input/output ports (j=natural number not less than 2). Therefore, the same effects at described above are achieved.
According to a seventeenth aspect of the present invention, there is provided a convolutional interleaving method for performing convolutional interleaving on a data group in which the input/output data width is b bits, the depth, i.e., the number of data in bit width units, is m, the number of channels is n, and the maximum channel number is C (n=integer satisfying the relation 0xe2x89xa6nxe2x89xa6C, b,m,C=natural numbers), and the method comprises: employing delay means which performs a delay of nT (xcfx84=a predetermined amount of delay, T greater than 0) for data of the n-th channel, and comprises first and second delay units; performing, by using the first delay unit, a delay of iS (S=a predetermined amount of delay, 0 less than Sxe2x89xa6T) on the i-th group amongst groups into which all the channels are grouped such that each group comprises at most k channels, the i-th group comprising channels from the ik-th channel to the ((i+1)kxe2x88x921)-th channel (k=natural number not larger than C, i=integer satisfying the relation 0xe2x89xa6ixe2x89xa6(integer part of (C/k)), (i+1)kxe2x88x921xe2x89xa6C); and performing, by using the second delay unit, a delay equivalent to a deficiency in the delay of the first delay unit for the delay of nT to be given to the data of the n-th channel. Therefore, delays to be commonly generated between channels in each group are generated together by the first delay unit, and delays including differences in delays between the channels are individually generated by the second delay unit, whereby control and structure of the delay means can be simplified.
According to an eighteenth aspect of the present invention, in the convolutional interleaving method of the seventeenth aspect, C is an odd number, k is 2, S and T satisfy the relation S=T, and the second delay unit performs a delay of T for the (2h+1)-th channel (h=integer satisfying the relation 0xe2x89xa62h+1xe2x89xa6C) and does not perform a delay for the 2h-th channel. Therefore, delays to be commonly generated between two channels in each group are generated together by the first delay unit, and a difference in delays between the two channels is generated for only one of these two channels by the second delay unit, whereby control and structure of the delay means can be simplified.
According to a nineteenth aspect of the present invention, there is provided a convolutional interleaving method for performing convolutional interleaving on a data group in which the input/output data width is b bits, the depth, i.e., the number of data in bit width units, is m, the number of channels is n, and the maximum channel number is C (n=integer satisfying the relation 0xe2x89xa6nxe2x89xa6C, b,m,Cxe2x89xa6natural numbers), and the method comprises: employing first storage means which is able to store data having a data width of jxc3x97b bits (j=natural number not less than 2); distributing input data to bit connecting means, second storage means, or output data control means by using input data control means; delaying output data from the input data control means by using the second storage means; combining output data from the input data control means and output data from the second (storage means by using the bit connecting means to generate data to be input to the first storage means having a data width of jxc3x97b bits; generating addresses of the first storage means by address generating means; converting output data from the first storage means into convolutionally interleaved data having a data width of b bits, by using bit separating means; and outputting output data from the bit separating means by using the output data control means. Therefore, the RAM address generating means is optimized, whereby the area of the address generating circuit is minimized and the frequency of access to the RAM is reduced. Thereby, convolutional interleaving can be performed with the minimum power consumption and, moreover, it can be performed even with a RAM operating at a low frequency.
According to a twentieth aspect of the present invention, in the conventional interleaving method of the nineteenth aspect, the address generating means performs address generation such that the first storage means performs a delay of iS (S=a predetermined amount of delay, 0 less than S) on the i-th group amongst group sinto which all the channels are grouped such that each group comprises at most k channels, the i-th group comprising channels from the ik-th channel to the ((i+1)kxe2x88x921)-th channel (k=natural number not larger than C, i=integer satisfying the relation 0xe2x89xa6ixe2x89xa6(integer part of (C/k)), (i+1)kxe2x88x921xe2x89xa6C); the second storage means has a capacity sufficient to perform a delay equivalent to a deficiency in the delay of the first storage means for the delay of nT (T=a predetermined amount of delay, Sxe2x89xa6T) to be given to the data of the n-th channel; and channel switching is performed every time data of b bits and depth m is input, such that the channel of data input to the first storage means and the second storage means is identical in channel number to the channel of the data output from the first storage means. Therefore, the same effects as mentioned above are achieved.
According to a twenty-first aspect of the present invention, in the convolutional interleaving method of the twentieth aspect, C is an odd number, k is 2, S and T satisfy the relation S=T, and the second delay unit performs a delay of T for the (2h+1)-th channel (h=integer satisfying the relation 0xe2x89xa62h+1xe2x89xa6C) and does not perform a delay for the 2h-th channel. Therefore, the same effects as described above are achieved.
According to a twenty-second aspect of the present invention, there is provided a convolutional deinterleaving method for performing convolutional deinterleaving on a data group in which the input/output data width is b bits, the depth, i.e., the number of data in bit width units, is m, the number of channels is n, and the maximum channel number is C (n=integer satisfying the relation 0xe2x89xa6nxe2x89xa6C, b,m,C=natural numbers), and the method comprises: employing delay means which performs a delay of (Cxe2x88x92n)T (T=a predetermined amount of delay, T greater than 0) for data of the n-th channel, and comprises first and second delay units; performing, by using the first delay unit, a delay of (Cxe2x88x92i)iS (S=a predetermined amount of delay, 0 less than Sxe2x89xa6T) on the i-th group amongst groups into which all the channels are grouped such that each group comprises at most k channels, the i-th group comprising channels from the ik-th channel to the ((i+1)kxe2x88x921)-th channel (k=natural) number not larger than C, i=integer satisfying the relation 0xe2x89xa6ixe2x89xa6(integer part of (C/k)), (i+1)kxe2x88x921xe2x89xa6C); and performing, by using the second delay unit, a delay equivalent to a deficiency in the delay of the first delay unit for the delay of (Cxe2x88x92n)T to be given to the data of the n-th channel. Therefore, delays to be commonly generated between channels in each group are generated together by the first delay unit, and delays including differences in delays between the channels are individually generated by the second delay unit, whereby control and structure of the delay means can be simplified.
According to a twenty-third aspect of the present invention, in the convolutional deinterleaving method of the twenty-second aspect, C is an odd number, k is 2, S and T satisfy the relation S=T, and the second delay unit performs a delay of T for the (2h+1)-th channel (h=integer satisfying the relation 0xe2x89xa62h+1xe2x89xa6C) and does not perform a delay for the 2h-th channel. Therefore, delays to be commonly generated between two channels in each group are generated together by the first delay unit, and a difference in delays between the two channels is generated for only one of these two channels by the second delay unit, whereby control and structure of the delay means can be simplified.
According to a twenty-fourth aspect of the present invention, there is provided a convolutional deinterleaving method for performing convolutional deinterleaving on a data group in which the input/output data width is b bits, the depth, i.e., the number of data in bit width units, is m, the number of channels is n, and the maximum channel number is C (nxe2x88x92integer satisfying the relation 0xe2x89xa6nxe2x89xa6C, b,m,C=natural numbers), and the method comprises: employing first storage means which is able to store data having a data width of jxc3x97b bits (j=natural number not less than 2); distributing input data to bit connecting means, second storage means, or output data control means by using input data control means; delaying output data from the input data control means by using the second storage means; combining output data from the input data control means and output data from the second storage means by using the bit connecting means to generate data to be input to the first storage means having a data width of jxc3x97b bits; generating addresses of the first storage means by address generating means; converting output data from the first storage means into convolutionally deinterleaved data having a data width of b bits, by using bit separating means; and outputting output data from the bit separating means by using the output data control means. Therefore, the RAM address generating means is optimized, whereby the area of the address generating circuit is minimized and the frequency of access to the RAM is reduced. Thereby, convolutional deinterleaving can be performed with the minimum power consumption and, moreover, it can be performed even with a RAM operating at a low frequency.
According to a twenty-fifth aspect of the present invention, in the convolutional deinterleaving method of the twenty-fourth aspect, the address generating means performs address generation such that the first storage means performs a delay of (Cxe2x88x92i)S (S=a predetermined amount of delay, 0 less than S) on the i-th group amongst groups into which all the channels are grouped such that each group comprises at most k channels, the i-th group comprising channels from the ik-th channel to the ((i+1)kxe2x88x921)-th channel (k=natural number not larger than C, i=integer satisfying the relation 0xe2x89xa6ixe2x89xa6(integer part of (C/k)), (i+1)kxe2x88x921xe2x89xa6C); the second storage means has a capacity sufficient to perform a delay equivalent to a deficiency in the delay of the first storage means for the delay of (Cxe2x88x92n)T (T=a predetermined amount of delay, Sxe2x89xa6T) to be given to the data of the n-th channel; and channel switching is performed every time data of b bits and depth m is input, such that the channel of data input to the first storage means and the second storage means is identical in channel number to the channel of the data output from the first storage means. Therefore, the same effects as described above are achieved.
According to a twenty-sixth aspect of the present invention, in the convolutional interleaving method of the twenty-fifth aspect, C is an odd number, k is 2, S and T satisfy the relation S=T, and the second delay unit performs a delay of T for the (2h+1)-th channel (h=integer satisfying the relation 0xe2x89xa62h+1xe2x89xa6C) and does not perform a delay for the 2h-th channel. Therefore, the same effects as described above are achieved.